1. Field of the Invention
The present invention relates to a solid-state image pickup device, and more particularly to a technology adapted to an active XY address type solid-state image pickup device among solid-state image pickup devices compatible with the CMOS manufacturing processes (the so-called CMOS sensors) or to a CCD sensor.
2. Description of the Prior Art
The conventional solid-state image pickup devices of the transfer layer type that transfer photoelectrically converted signal charges can roughly be classified into those of MOS type and CCD type. These solid-state image pickup devices, especially the solid-state image pickup devices of the CCD type, have been applied in recent years to camera-integrated VTRs, digital cameras, facsimile equipment, and the like, and are still in the process of technical development for improvement of their characteristics.
A CCD sensor is equipped with a photoelectric conversion part in which photoelectric conversion elements corresponding to pixels are arranged two-dimensionally, and pixel signals that are converted to electrical charges by means of the photoelectric conversion part are read sequentially by a vertical transfer CCD and a horizontal transfer CCD.
A CMOS sensor does not employ CCDs for vertical and horizontal transfers, and reads pixels selected by selection lines formed of aluminum wires or the like, as in the case of a memory device.
Here, in comparison to the CCD sensor that requires a plurality of positive and negative power supply potentials, the CMOS sensor can be driven by a single power supply, and hence it is possible to reduce the power consumption and the operating voltage as compared with the CCD sensor.
Moreover, in contrast to the difficulty for the CCD sensor that adopts intrinsic manufacturing processes in applying the manufacturing processes, as they are, of the CMOS circuit, the manufacturing processes of CMOS circuits are readily adopted for the CMOS sensor. Accordingly, in the CMOS sensor it is possible to form simultaneously a logic circuit, an analog circuit, an analog to digital conversion circuit, and the like by the CMOS processes that are widely in use for the manufacture of a processor, a semiconductor memory such as DRAM, a logic circuit, or the like. In short, the CMOS sensor can be formed on the same semiconductor chip along with a semiconductor memory and a processor, or can share the same production line with a semiconductor memory or a processor. An example of the CMOS sensor is shown in FIG. 12.
In FIG. 12 which shows an image-pickup element (CMOS sensor) labeled with symbol 100, the CMOS sensor 100 comprises a timing generating part 102, an image sensor part 101, a vertical scanning part 103 and a horizontal scanning part 104 for selecting pixel outputs, an analog signal processing part 105, an A/D part (A/D conversion part) 109 for performing analog to digital conversion, a digital signal processing part 107 for converting a digitized signal into an output signal, and an interface part (IF part) 108 for outputting digital image data to the outside as well as receiving a command from the outside.
The image sensor part 101 is an assembly of fundamental cells of the CMOS sensor as will be described later, and the vertical scanning part 103 is for vertically controlling the fundamental cells of the image sensor part 101, the horizontal scanning part 104 is for horizontally controlling the fundamental cells of the image sensor part 101, and these scanning parts perform respective scanning control by means of timing signals output from the timing generating part 102.
The analog signal processing part 105 applies a required processing to an image signal read from the image sensor part 101 to output the result to the A/D conversion part 109, the A/D conversion part 109 converts the image signal into a digital signal to output the result to the digital signal processing part 107, and the digital signal processing part 107 outputs the image signal to the IF part 108.
The IF part 108 outputs digital image data output via the digital signal processing part 107, and is capable of inputting a command from the outside. With this arrangement, the IF part 108 controls various constituent components so as to be able to control the mode, output signal form, signal output timing or the like of the image-pickup element 100 in response to the command.
Here, the vertical scanning part 103, the horizontal scanning part 104, the A/D conversion part 109, the digital signal processing part 107, the IF part 108, and the like constitute a logic circuit part 106. Moreover, a configuration may be adopted in which the digital signal processing part 107 is provided with a memory for storing one or plural lines, one or plural blocks, or one or plural frames of image data to be utilized for signal processing in the digital signal processing part 107.
Next, a part of the conventional fundamental cells in the image sensor part 101 and the logic circuit part 106, of the CMOS sensor 100 will be shown in FIG. 13.
In FIG. 13, symbol 10 is the CMOS sensor being the fundamental cells, 11 is a P type silicon substrate, 12 is a P type well, 13 is a field oxide film for element isolation, 14 is an N type region (photoelectric conversion region) which is to be a photodiode, 15 is an N+ type region (diffused layer) which is to be a reset drain, 16, 16A, and 16B are gate SiO2 films. Moreover, symbol 17 is a polycrystalline silicon film which is to be a reset gate, 17A is the gate film of a MOSFET of a source follower amplifier, 17B is the gate film of a MOSFET as a horizontal selection switch, 15A is an N+ type region which is to be the source or drain of the MOSFET of the source follower amplifier, 15B is an N+ type region which is to be the source or drain of the MOSFET of the source follower amplifier as well as the source or drain of the MOSFET as the horizontal selection switch, 15C is a P type region which is to be the source or drain of a load MOSFET, 18A, 18B, 18C, 19A, and 19B are wiring layers, and 21 is a metal film which is to be a light shielding film that defines an opening part through which light is made incident.
In the CMOS sensor 10, the photoelectric conversion region 14 is connected to the gate 17A of the MOSFET constituting the source follower amplifier via the wiring layer 18B or the like, by which the N+ type region 15A which is to be the source or drain of the MOSFET is linked to the source or drain of the MOSFET as the horizontal selection switch so that these MOSFETs are connected. Consequently, the N+ type region 15B which is to be the source or drain of the MOSFET is linked and connected to the source or drain of the load MOSFET forming the source follower amplifier. The N+ type region 15B which is to be the source or drain of both MOSFETs is connected to the source or drain of a dark output transfer MOSFET and a bright output transfer MOSFET, respectively, and the sources or drains of the dark output transfer MOSFET and the bright output transfer MOSFET are connected to a dark output storage capacitor and a bright output storage capacitor, respectively.
Between the photoelectric conversion region 14 and the light shielding film 21 there are provided a layer insulating film 22 and a plurality of wiring layers 16, 16A, 16B, 17, 17A, 17B, 18A, 18B, 18C, 19A, 19B, and 19C, as shown in FIG. 13.
The logic circuit part 106 is formed adjacent to, for example, the image sensor part 101 as shown in FIG. 13. In the part 106, a P type well 32A and an N type well 32B are formed in the P type silicon substrate 11, an N+ type region 33A and a P+ type region 33B that are to be diffused layers are provided in the well regions 32A and 32B, respectively, gates 34A and 34B formed of polycrystalline silicon are provided above these regions, metal films 35A, 35B, 36A, and 36B that are to be wiring layers are provided above the gates, and a light shielding layer 20 covering all of these is provided in the topmost part.
The CMOS sensor 10 with the above configuration operates as in the following.
First, as shown in FIG. 14A, the potential of the photoelectric conversion region 14 is set at a power supply voltage VDD by applying a high pulse ØR to the reset gate 17 to reset the signal charge of the photoelectric conversion region 14. Next, a low pulse ØR is applied to the reset gate 17 for preventing blooming as shown in FIG. 14C.
During storage of signal charges, when electron-hole pairs are generated in the region below the photoelectric conversion region 14 by light whose incident position is regulated by the opening part 23 of the light shielding film 21, electrons are stored in a depletion layer below the photoelectric conversion region 14, and holes are discharged through the P type well 12. In FIG. 14C, the region with deeper potential than the power supply voltage VDD indicated by crisscrossed hatching shows that the region is not depleted. Since a potential barrier is formed between the depletion layer formed in the P type well 12 below the photoelectric conversion region 14 and the N+ type region 15 which is to be a floating diffused layer by a control MOSFET, electrons remain in the region below the photoelectric conversion region 14 during storage of the photoelectric charges as shown in FIG. 14C.
Following that, the potential of the photoelectric conversion region 14 varies corresponding to the number of stored electrons, the change in the potential is output to the drain (N+ type region) 15B of the horizontal selection switch MOSFET via the source (N+ type region) of the source follower amplifier MOSFET by means of the operation as a source follower, and the potential is output from the wiring layer 19B which acts as the output terminal of the source follower amplifier. In this way, it is possible to obtain a photoelectric conversion characteristic of an excellent linearity.
Here, kTC noise due to reset is generated in the N+ type region 15 which is to become a floating diffused layer. However, the noise can be removed by taking the difference between the bright output, and the dark output that has been accumulated prior to the signal electron transfer.
In recent years, design of a semiconductor device as a “system on chip (SOC)” that includes desired system/element functional operations in a single LSI body by unifying various pieces of hardware (H/W integration) such as a CPU, memory, standard/dedicated macro, analog circuit, and image sensor part, and various pieces of software (S/W integration) such as image compression and expansion, sound processing, and communication functions, has been tried. In order to manufacture a solid-state image pickup device as an SOC, the logic circuit part 106 is manufactured utilizing technologies accumulated in the past, and adaptation of a hybrid technology that integrates different processes on a single chip to form the solid-state image pickup device has been in demanded.
Here, there has been a demand to obtain the CMOS sensor as an SOC by forming an image sensor part 101 simultaneous with the logic circuit part 106 through utilization of CMOS processes by standard parameters that are widely in use in the formation of processors, semiconductor memories such as DRAM, logic circuits, or the like. There has been a demand to share the production line with semiconductor memories, processors or the like by forming these components on one chip in a single process flow.
In accordance with such demands, in the logic circuit part 106, the light shielding layer 20 is provided at the highest position of each element. In other words, a metal layer which is to become the light shielding layer 20 is formed above the wiring layers 35A, 35B, 36A, and 36B in order to effect light shielding without changing the arrangement of the wiring layers 35A, 35B, 36A, and 36B that are given the existing structure.
In the structure of the CMOS sensor 10 in the above, the light shielding layer 20 and the light shielding film 21 are provided at the topmost position as an integrated body. Since the layer insulating film 22 and a plurality of wiring layers 16, 16A, 16B, 17, 17A, 17B, 18A, 18B, 18C, 19A, 19B, and 19C exist between the light shielding film 21 that regulates the opening part 23 and the photoelectric conversion region 14 above the silicon substrate 11, the spacing L0 between the light shielding film 21 and the photoelectric region 14 becomes several μm which is very large in comparison to the wavelength (in the range of 350 to 770 nm) of the visible rays. As a result, incident beams 25 diffracted by the diffraction effect of the beams incident through the opening part 23 are made incident on the periphery of the photoelectric conversion region 14 as shown in FIG. 15.
Consequently, according to such a structure of the CMOS sensor, false signals generated by the photoelectric conversion effect of the light incident on the periphery of the photoelectric conversion region 14 leaks into adjacent photoelectric conversion region, and causes the problem of degradation of the S/N of image signals.
As counter measures against the false signals there has been proposed such a technology as to set the dimension (for example, the width W0) of the opening part 23 to be smaller compared with the dimension (for example, the width W14) of the photoelectric conversion region 14. However, in such a case, the quantity of light incident on the photoelectric conversion region 14 is reduced, and results in the problem of the reduction in the sensitivity.
Furthermore, when a means is adopted to provide, for example, the light shielding film 21 at a position below the wiring layers 18A, 18B, 18C, 19A, 19B, and 19C as countermeasures against the false signals, and as a solution to the reduction in the quantity of light on the photoelectric conversion region 14 and to the reduction in the sensitivity, it becomes necessary also in the logic circuit part 106 to place the light shielding layer 20 below the positions of the metal layers 35A, 35B, 36A, 36B, or the like because the light shielding layer 20 and the light shielding film 21 are formed integrally. This leads to the problem of the necessity for designing the logic circuit part 106 entirely anew.
Besides, in this case, there is a possibility in its manufacturing process of changing the existing parameters for manufacture and design, which results in the problem that the conversion to an SOC is difficult.
For these reasons, it may become impossible to exhibit the characteristics of the CMOS sensor such as, the simultaneous formation of a logic circuit, analog circuit, A/D conversion circuit, or the like, the formation of the image sensor part 101 on the same semiconductor chip as the semiconductor memory and the processor, and the possibility of sharing the production line with the semiconductor memory and the processor. As a result, there has been a possibility of being forced to adopt an intrinsic process for the CMOS sensor similar to the CCD sensor, and is unable to make active use of the characteristic of the CMOS sensor that the manufacturing cost is reducible.